As a Digital Design Engineer, you can expect to:
- Contribute to the development of one or more Co-processor units, industry standard, high-speed serial bus interfaces for Marvell’s next generation Multi-core embedded ARM processor family targeted at Networking, Storage, Security, and Wireless applications in the state-of-the-art deep sub-micron CMOS process technologies.
- Write specifications for the relevant block, micro-architecture of the block, design implementation using RTL coding techniques, Synthesis, place & route and timing sign off.
- Shape the micro-architecture of the chip.
- Review the verification test plan, coverage analysis and full chip simulation plus debug.
Key skills & requirements:
- Electrical/ Computer Engineering or similar disciplines.
- Knowledge of scripting languages such as Perl/Python Tcl and UNIX shell etc. is desirable
- RTL design experience, Synthesis static timing closure, formal verification, gate-level simulations, and block-level function verification
- Experience in designing low power, high-speed (>1 GHz), and high- performance ASICs / SOCs